On the Complexity of Scheduling Problems for Parallel/Pipelined Machines
IEEE Transactions on Computers
The hierarchical task graph as a universal intermediate representation
International Journal of Parallel Programming
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Communication synthesis and HW/SW integration for embedded system design
Proceedings of the 6th international workshop on Hardware/software codesign
Proceedings of the 6th international workshop on Hardware/software codesign
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Theory and Practice in Parallel Job Scheduling
IPPS '97 Proceedings of the Job Scheduling Strategies for Parallel Processing
An evolutionary approach to system-level synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Ant Colony Optimization
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Genetic algorithms for hardware-software partitioning and optimal resource allocation
Journal of Systems Architecture: the EUROMICRO Journal
A performance study of multiprocessor task scheduling algorithms
The Journal of Supercomputing
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
Proceedings of the 45th annual Design Automation Conference
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor
Proceedings of the 45th annual Design Automation Conference
Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology - Fuzzy theory and technology with applications
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ant colony optimization for resource-constrained project scheduling
IEEE Transactions on Evolutionary Computation
Ant system: optimization by a colony of cooperating agents
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A systematic approach to classify design-time global scheduling techniques
ACM Computing Surveys (CSUR)
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Parallel and Distributed Computing
Exploiting domain knowledge in system-level MPSoC design space exploration
Journal of Systems Architecture: the EUROMICRO Journal
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To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtaining low-quality solutions. In this paper, we propose an ant colony optimization (ACO) heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. We compare our approach with several other heuristics, including simulated annealing, tabu search, and genetic algorithms, on the performance to reach the optimum value and on the potential to explore the design space. We show that our approach obtains better results than other heuristics by at least 16% on average, despite an overhead in execution time. Finally, we validate the approach by scheduling and mapping a JPEG encoder on a realistic target architecture.