Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Proceedings of the 6th international workshop on Hardware/software codesign
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
Proceedings of the 37th Annual Design Automation Conference
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
HW / SW partitioning approach for reconfigurable system design
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Improving functional density through run-time circuit reconfiguration
Improving functional density through run-time circuit reconfiguration
Configuration management techniques for reconfigurable computing
Configuration management techniques for reconfigurable computing
Proceedings of the 42nd annual Design Automation Conference
Power-Performance Trade-Offs for Reconfigurable Computing
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal reconfiguration sequence management
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A system-level approach to hardware reconfigurable systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Introduction to Mathematical Programming: Applications and Algorithms
Introduction to Mathematical Programming: Applications and Algorithms
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Systems and Software
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Integrating real-time inter-task communication channels into hardware-software codesign
Microprocessors & Microsystems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust Software Partitioning with Multiple Instantiation
INFORMS Journal on Computing
International Journal of Applied Evolutionary Computation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability imposes strict placement constraints such that even exact system-level partitioning (and scheduling) formulations are not guaranteed to be physically realizable due to placement infeasibility. We first present an exact approach for hardware-software (HW-SW) partitioning that guarantees correctness of implementation by considering placement implications as an integral aspect of HW-SW partitioning. Our exact approach is based on integer linear programming (ILP) and considers key issues such as configuration prefetch for minimizing schedule length on the target single-context device. Next, we present a physically aware HW-SW partitioning heuristic that simultaneously partitions, schedules, and does linear placement of tasks on such devices. With the exact formulation, we confirm the necessity of physically-aware HW-SW partitioning for the target architecture. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and with a popular, but placement-ua-naware scheduling heuristic for a large set of over a hundred tests. Our final set of experiments is a case study of JPEG encoding--we demonstrate that our focus on physical considerations along with our consideration of multiple task implementation points enables our approach to be easily extended to handle heterogenous architectures (with specialized resources distributed between general purpose programmable logic columns). The execution time of our heuristic is very reasonable--task graphs with hundreds of nodes are processed (partitioned, scheduled, and placed) in a couple of minutes.