COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
IEEE Transactions on Computers
ATLANTIS - A Hybrid FPGA/RISC Based Re-configurable System
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Configurable computing: the catalyst for high-performance architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Critical path driven cosynthesis for heterogeneous target architectures
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Efficient search space exploration for HW-SW partitioning
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design Space Exploration for Dynamically Reconfigurable Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for core-level modeling and design of reconfigurable computing algorithms
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
A BBN-based framework for adaptive IP-reuse
Proceedings of the 6th FPGAworld Conference
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This paper presents a Genetic Algorithm (GA) based approach for Hardware/Software partitioning targeting an architecture composed of a processor and a dynamically reconfigurable datapath (FPGA). From an acyclic task graph and a set of Area-Time implementation trade off points for each task, our GA performs HW/SW partitioning and scheduling such that the global application execution time is minimized. The efficiency of our GA is established through its application to an AC-3 decoder function and its performance is compared with a greedy algorithm.