Scheduling precedence graphs in systems with interprocessor communication times
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IEEE Transactions on Parallel and Distributed Systems
A comparison of list schedules for parallel processing systems
Communications of the ACM
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IEEE Transactions on Parallel and Distributed Systems
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DSC: Scheduling Parallel Tasks on an Unbounded Number of Processors
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Hardware-software co-synthesis of distributed embedded systems
Hardware-software co-synthesis of distributed embedded systems
A codesign experiment in acoustic echo cancellation: GMDFα
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Scheduling with optimized communication for time-triggered embedded systems
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Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication
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Bus access optimization for distributed embedded systems based on schedulability analysis
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HW / SW partitioning approach for reconfigurable system design
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Highly-cited ideas in system codesign and synthesis
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Embedded Systems Design
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This paper presents a critical path driven algorithm to produce a static schedule of a single-rate system onto a heterogeneous target architecture. Our algorithm is a list based scheduling algorithm which concurrently assigns tasks to processors and allocates nets to interprocessor communication. Experimental results show that our algorithm is able to find good results, as compared to other methods, in small amount of CPU time.