Automatic layout of analog and digital mixed macro/standard cell integrated circuits
Automatic layout of analog and digital mixed macro/standard cell integrated circuits
Kernel scheduling in reconfigurable computing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
HW / SW partitioning approach for reconfigurable system design
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
An efficient simulated annealing schedule
An efficient simulated annealing schedule
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Run-time HW/SW scheduling of data flow applications on reconfigurable architectures
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Evaluation of runtime task mapping using the rSesame framework
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
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By incorporating reconfigurable hardware in embedded system architectures it has become easier to satisfy the performance constraints of demanding applications while lowering system cost. In order to evaluate the performance of a candidate architecture, the nodes (tasks) of the data flow graphs that describe an application must be assigned to the computing resources of the architecture: programmable processors and reconfigurable FPGAs, whose run-time reconfiguration capabilities must be exploited. In this paper we present a novel design exploration tool-based on a local search algorithm with global convergence properties-which simultaneously explores choices for computing resources, assignments of nodes to these resources, task schedules on the programmable processors and context definitions for the reconfigurable circuits. The tool finds a solution that minimizes system cost while meeting the performance constraints; more precisely it lets the designer select the quality of the optimization (hence its computing time) and finds accordingly a solution with close-to-minimal cost.