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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
System-level synthesis of low-power hard real-time systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Power modeling for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Schedulability-driven performance analysis of multiple mode embedded real-time systems
Proceedings of the 37th Annual Design Automation Conference
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis of low-power control-flow intensive circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design Space Exploration for Dynamically Reconfigurable Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
A parallel configuration model for reducing the run-time reconfiguration overhead
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of VLSI Signal Processing Systems
Energy efficient co-scheduling in dynamically reconfigurable systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Design flow instantiation for run-time reconfigurable systems: a case study
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithmic aspects for power-efficient hardware/software partitioning
Mathematics and Computers in Simulation
A task graph execution manager for reconfigurable multi-tasking systems
Microprocessors & Microsystems
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Hardware supported task scheduling on dynamically reconfigurable SoC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a multi-objective hardware-software co-synthesis system for multi-rate, real-time, low powered distributed embedded systems consisting of dynamically reconfigurable FPGAs, processors, and other system resources. We use an evolutionary algorithm based framework for automatically determining the quantity and type of different system resources, and then assigning tasks to different processing elements (PEs) and task communications to communication links. For FPGAs, we propose a two-dimensional, multi-rate cyclic scheduling algorithm, which determines task priorities based on real-time constraints and reconfiguration overhead information, and then schedules tasks based on the resource utilization and reconfiguration condition in both space and time. The FPGA schedulers integrated in a list-based system scheduler. To the best of our knowledge, this is the first multi-objective co-synthesis system, which uses dynamically reconfigurable devices to synthesize a distributed embedded system, to target simultaneous optimization of system price and power. Exper mental results indicate that our method can reduce schedule length by an average of 41.0% and reconfiguration power by an average of 46.0% compared to the previous method. It also yields multiple system architectures which trade off system price and power under real-time constraints.