Statistical design space exploration for application-specific unit synthesis
Proceedings of the 38th annual Design Automation Conference
Input space adaptive design: a high-level methodology for energy and performance optimization
Proceedings of the 38th annual Design Automation Conference
A symbolic approach for the combined solution of scheduling and allocation
Proceedings of the 15th international symposium on System Synthesis
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Leakage Power Analysis and Reduction during Behavioral Synthesis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
Slack analysis in the system design loop
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
| Hi-index | 0.03 |
In this paper, we present a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process. Experimental results for a number of control-flow intensive and data-dominated benchmarks demonstrate power reduction of up to 62% (58%) when compared to Vdd-scaled area-optimized (delay-optimized) designs. The area overheads over area-optimized designs are less than 39%, whereas the area savings over delay-optimized designs are up to 40%