CHOP: A constraint-driven system-level partitioner
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
ACM Transactions on Design Automation of Electronic Systems (TODAES)
COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOCSYN: multiobjective core-based single-chip system synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Power modeling for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Genetic Algorithm and Graph Partitioning
IEEE Transactions on Computers
Fast Allocation of Processes in Distributed and Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Hardware Software Partitioning Using Genetic Algorithm
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Hardware-software co-synthesis of distributed embedded systems
Hardware-software co-synthesis of distributed embedded systems
High-level synthesis of low-power control-flow intensive circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
Battery-aware code partitioning for a text to speech system
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Computers and Electrical Engineering
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
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In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The system-level specification is assumed to be given as a set of task graphs. The goal is to partition the task graphs so that each partitioned segment is implemented as an SOC and the embedded system is realized as a distributed system of SOCs. Unlike most previous synthesis and partitioning tools, this technique merges partitioning and system synthesis (allocation, assignment, and scheduling) into one integrated process; both are implemented within a genetic algorithm. Genetic algorithms can escape local minima and explore the partitioning and synthesis design space efficiently. Through integration with an existing SOC synthesis tool, the proposed partitioning technique satisfies both the hard real-time constraints and the SOC area constraint of each partitioned segment. Under these constraints, our tool performs multi-objective optimization. Thus, with a single run of the tool, it produces multiple distributed SOC-based embedded system architectures that trade off the overall distributed system price and power consumption. Experimental results show the efficacy of our technique.