Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
Computers and Electrical Engineering
Using adaptive routing to compensate for performance heterogeneity
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors
IEEE Computer Architecture Letters
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Fast and efficient processor allocation algorithm for torus-based chip multiprocessors
Computers and Electrical Engineering
Computers and Electrical Engineering
Combined heuristics for synthesis of SOCs with time and power constraints
Computers and Electrical Engineering
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Abstract: Process variations in advanced nodes introduce significant core-to-core performance differences in multi-core architectures. These intra-die variations have a strong spatial correlation, leading to potential large variations among clusters of cores. Isolating each core with its own frequency and voltage island improves the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-core communication suffers from additional cross-clock-domain latencies that can offset the performance benefits. This work proposes the concept of the configurable, variable-size frequency and voltage domain, and it is described in the context of a tile-based multi-core architecture. The number of domains is determined on a chip-by-chip basis based on process variation. We observe that the optimal size of the frequency and voltage domain can range from full die to single core depending on the workload characteristics and the degree of process variation.