Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability

Authors:
Xiaoyao Liang;Ramon Canal;Gu-Yeon Wei;David Brooks
Affiliations:
Harvard University;Universitat Politècnica de Catalunya;Harvard University;Harvard University
Venue:
IEEE Micro
Year:
2008

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Abstract

With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.