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Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Networks on chip
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Characterizing the Cell EIB On-Chip Network
IEEE Micro
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A synergetic operating unit on NoC layer for CMP system
International Journal of High Performance Systems Architecture
Network interface design based on mutual interface definition
International Journal of High Performance Systems Architecture
A networks-on-chip emulation/verification framework
International Journal of High Performance Systems Architecture
Computers and Electrical Engineering
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip
Computers and Electrical Engineering
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Many on-chip network circuit and architecture techniques are incompatible with modern design flows, making them unsuitable for use in systems-on-chip. This paper presents a networks-on-chip (NoC) architecture design space exploration method for multi-processor systems-on-chip architecture. The NoC architecture design space is designed with a Layer-Interactive-Building block (LIB) methodology that is divided into three layers: application layer, link/network layer, and physical layer. The suggested LIB design paradigmatic philosophy provides modular building block structure in both hardware and software and the protocols for their interconnection in the three architecture layers. Using LIB the designer can easily select these building blocks to build application-specific NoCs to meet different application requirements such as media, graphic, software radio and communication network applications. The LIB provides the NoC building blocks, architecture interacting systems-on-chip components, the programming models and application mapping strategies. The LIB can be used as a complementary library and tools for future on-chip interconnection network design.