Fast fourier transforms: a tutorial review and a state of the art
Signal Processing
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
ARM MPCore; The streamlined and scalable ARM11 processor core
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Anatomy of a Portable Digital Mediaprocessor
IEEE Micro
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Coarse grain data flow graph (CGDFG) model based on message passing mechanism guides the parallel programming for the chip multiprocessor (CMP) system with distributed memory in our work. Parallel threads are exploited, encapsulated in objects and mapped onto the different processors according to the CGDFG principles. Efficient scheduling and synchronisation mechanisms with lower overhead are needed to maintain the processors running objects concurrently and synchronously. A hardware/software approach – synergetic operating unit (SOU) is proposed in this paper to manage the object scheduling and synchronisation for the lightweight CMP system. Compared with the original software approach this solution reduces the run-time object scheduling and synchronisation overhead effectively, thereby, meeting the requirements of running hard real-time applications. The hardware synergetic operating unit is situated in the link/network layer of networks-on-chip (NoC), which takes up about 14.5% area of the NoC and can run at a clock rate of 1,176 MHz (TSMC90 CMOS process technology). These two points make the SOU module to be easily integrated as a sub net of the NoC for CMP system.