Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Networks on chip
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Characterizing the Cell EIB On-Chip Network
IEEE Micro
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a novel network interface design method, referred to as mutual interface definition based method. It decouples resource dependent part (RDP) from resource independent part (RIP) by mutual interface definition. These two parts can be designed independently, thus the design flexibility and reusability of network interface can be enhanced. Moreover, a network interface component library consisting of multiple RDP and RIP components is proposed to be built. The networks-on-chip designers can choose appropriate components from the library to construct network interface design. From the perspective of RDP, the network interface achieves backward compatibility with the existing protocols such as AMBA AHB and OCP. From the perspective of RIP, the network interface provides a configurable structure supporting multicast transfer and adaptive routing algorithm extensions. The proposed network interface designs are implemented in TSMC 90-nm CMOS standard cell technology and can work at the frequency of 1.12 GHz to 1.35 GHz.