Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Extended design reuse trade-offs in hardware-software architecture mapping
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Test in the Emerging Intellectual Property Business
IEEE Design & Test
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Embedded Test and Debug of Full Custom and Synthesizable Microprocessor Cores
ETW '00 Proceedings of the IEEE European Test Workshop
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Power-efficient flexible processor architecture for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A modular simulation framework for architectural exploration of on-chip interconnection networks
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Case Study in Networks-on-Chip Design for Embedded Video
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-Visibility Debug-By-Design for FPGA Platforms
The Journal of Supercomputing
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Automated throughput-driven synthesis of bus-based communication architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
FABSYN: floorplan-aware bus architecture synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions
Journal of VLSI Signal Processing Systems
Proceedings of the 2007 ACM symposium on Applied computing
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Design and implementation of a reconfigurable arbiter
SSIP'07 Proceedings of the 7th WSEAS International Conference on Signal, Speech and Image Processing
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Extending open core protocol to support system-level cache coherence
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
A Trojan-resistant system-on-chip bus architecture
MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
Implementation of a self-motivated arbitration scheme for the multilayer ARB busmatrix
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
Heterogeneous integration to simplify many-core architecture simulations
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service
Proceedings of the 49th Annual Design Automation Conference
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Advanced RISC Machines Limited designs and licenses Intellectual Property in the form of low-power, small die-area, microprocessor macro-cells and peripherals. These components are combined into a wide range of embedded control integrated circuits, and it is important to ARM's business to make the job of designing a particular controller as simple as possible. AMBA, ARM's Advanced Micro-controller Bus Architecture is the result of five years of development of embedded controller and Application Specific Standard Parts (ASSPs). AMBA defines both a bus specification and a technology independent methodology for designing, implementing and testing customized high-integration embedded controllers. The bus interface is rationalized to ensure right-first-time designs and improve product migration to next-generation cached microprocessors and multiprocessor designs. A further benefit of a well-defined on-chip bus specification is to facilitate the design and exchange of components between ARM Semiconductor licensees and peripheral developers. This paper outlines the issues facing designers when integrating RISC cores into integrated circuits, describes the rationale and specific bus protocols developed for such embedded processor applications and introduces novel approaches to macro-cell test and bus partitioning for power minimization. Finally future plans are introduced for extending the bus for products integrating on-chip DRAM and higher-bandwidth external memory.