Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
Towards trojan-free trusted ICs: problem analysis and detection scheme
Proceedings of the conference on Design, automation and test in Europe
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
A Novel Sustained Vector Technique for the Detection of Hardware Trojans
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Sensitivity analysis to hardware Trojans using power supply transient signals
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
At-speed delay characterization for IC authentication and Trojan Horse detection
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Detecting malicious inclusions in secure hardware: Challenges and solutions
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
On-demand transparency for improving hardware Trojan detectability
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Hardware Trojan detection using path delay fingerprint
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Verifying the authenticity of chip designs with the DesignTag system
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
Proceedings of the 49th Annual Design Automation Conference
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Communications systems are increasingly reliant on system-on-chip (SoC) solutions. As the complexity and size of SoCs continues to grow, so does the risk of "Trojan" attacks, in which an integrated circuit (IC) design is surreptitiously and maliciously altered at some point during the design or manufacturing process. Despite the risks that such an attack entail, relatively little attention has been given in the literature to methods enabling detection of and response to run-time Trojan attacks. In the present paper, we present a Trojan-resistant system bus architecture suitable across a wide range of SoC bus systems. The system detects malicious bus behaviors associated Trojan hardware, protects the system and system bus from them and reports the malicious behaviors to the CPU. We show that use of this bus and associated embedded software is highly effective in reducing IC Trojan vulnerabilities without loss of bus performance.