At-speed delay characterization for IC authentication and Trojan Horse detection

  • Authors:
  • Jie Li;John Lach

  • Affiliations:
  • Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, USA;Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, USA

  • Venue:
  • HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
  • Year:
  • 2008

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Abstract

New attacker scenarios involving integrated circuits (ICs) are emerging that pose a tremendous threat to national security. Concerns about overseas fabrication facilities and the protection of deployed ICs have given rise to methods for IC authentication (ensuring that an IC being used in a system has not been altered, replaced, or spoofed) and hardware Trojan Horse (HTH) detection (ensuring that an IC fabricated in a non-secure facility contains the desired functionality and nothing more), but significant additional work is required to quell these treats. This paper discusses how a technique for precisely measuring the combinational delay of an arbitrarily large number of register-to-register paths internal to the functional portion of the IC can be used to provide the desired authentication and design alteration (including HTH implantation) detection. This low-cost delay measurement technique does not affect the main IC functionality and can be performed at-speed at both test-time and run-time.