Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
CAD-based security, cryptography, and digital rights management
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Techniques for Design and Implementation of Secure Reconfigurable PUFs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
At-speed delay characterization for IC authentication and Trojan Horse detection
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
A region based approach for the identification of hardware Trojans
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
SVD-Based Ghost Circuitry Detection
Information Hiding
Hardware Trojan horse detection using gate-level characterization
Proceedings of the 46th Annual Design Automation Conference
Consistency-based characterization for IC Trojan detection
Proceedings of the 2009 International Conference on Computer-Aided Design
A Survey of Hardware Trojan Taxonomy and Detection
IEEE Design & Test
ACM SIGDA Newsletter
A unified submodular framework for multimodal IC Trojan detection
IH'10 Proceedings of the 12th international conference on Information hiding
SoC: a real platform for IP reuse, IP infringement, and IP protection
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Matched public PUF: ultra low energy security platform
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Differential public physically unclonable functions: architecture and applications
Proceedings of the 48th Design Automation Conference
Integrated circuit security techniques using variable supply voltage
Proceedings of the 48th Design Automation Conference
Device aging-based physically unclonable functions
Proceedings of the 48th Design Automation Conference
Integrated circuit digital rights management techniques using physical level characterization
Proceedings of the 11th annual ACM workshop on Digital rights management
Robust passive hardware metering
Proceedings of the International Conference on Computer-Aided Design
Scalable segmentation-based malicious circuitry detection and diagnosis
Proceedings of the International Conference on Computer-Aided Design
Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection
Proceedings of the fifth ACM conference on Security and Privacy in Wireless and Mobile Networks
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
Proceedings of the 49th Annual Design Automation Conference
Can EDA combat the rise of electronic counterfeiting?
Proceedings of the 49th Annual Design Automation Conference
Provably complete hardware trojan detection using test point insertion
Proceedings of the International Conference on Computer-Aided Design
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Energy attacks and defense techniques for wireless systems
Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
VeriTrust: verification for hardware trust
Proceedings of the 50th Annual Design Automation Conference
The undetectable and unprovable hardware trojan horse
Proceedings of the 50th Annual Design Automation Conference
Scalable hardware trojan diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Gate-level characterization (GLC) is the process of characterizing each gate of an integrated circuit (IC) in terms of its physical and manifestation properties. It is a key step in the IC applications regarding cryptography, security, and digital rights management. However, GLC is challenging due to the existence of manufacturing variability (MV) and the strong correlations among some gates in the circuit. We propose a new solution for GLC by using thermal conditioning techniques. In particular, we apply thermal control on the process of GLC, which breaks the correlations by imposing extra variations concerning gate level leakage power. The scaling factors of all the gates can be characterized by solving a system of linear equations using linear programming (LP). Based on the obtained gate level scaling factors, we demonstrate an application of GLC, hardware Trojan horse (HTH) detection, by using constraint manipulation. We evaluate our approach of GLC and HTH detection on several ISCAS85/89 benchmarks. The simulation results show that our thermally conditioned GLC approach is capable of characterizing all the gates with an average error less than the measurement error, and we can detect HTHs with 100% accuracy on a target circuit.