Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Monitoring Temperature in FPGA based SoCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Leakage control in FPGA routing fabric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Variation-aware routing for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
GlitchLess: an active glitch minimization technique for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Analysis and modeling of CD variation for statistical static timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate-level characterization: foundations and hardware security applications
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal and power characterization of field-programmable gate arrays
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
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The impact of process variation (PV) in deep submicron CMOS technologies has raised major concerns for energy optimization efforts in FPGAs. We have developed a post-silicon leakage energy optimization scheme that raises the threshold voltage (by way of negative bias temperature instability (NBTI) aging) of the components that are either unused or not on the critical timing paths, thereby reducing the total leakage energy consumption. In order to obtain the input vectors for aging only the targeted transistors, we map the problem of minimizing leakage energy under timing constraints to an instance of the satisfiability (SAT) problem. We implemented low power designs targeting Xilinx Spartan6 FPGAs and analyzed the potential leakage power savings over a set of ITC99 and Opencores benchmarks. The analysis of the experimental results shows a substantial amount of potential leakage energy reduction with very small performance degradation.