Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Power-conscious high level synthesis using loop folding
DAC '97 Proceedings of the 34th annual Design Automation Conference
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Glitch power minimization by selective gate freezing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Influence of compiler optimizations on system power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A routing approach to reduce glitches in low power FPGAs
Proceedings of the 2009 international symposium on Physical design
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow.