Improving locality using loop and data transformations in an integrated framework
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Influence of compiler optimizations on system power
Proceedings of the 37th Annual Design Automation Conference
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Holistic Approach to System Level Energy Optimization
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2004 ACM symposium on Applied computing
GlitchLess: an active glitch minimization technique for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Compiler-directed leakage reduction in embedded microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Auto-tuning for energy usage in scientific applications
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing - Volume 2
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Optimizing for energy constraints is of critical importance due to the proliferation of battery-operated embedded devices. Thus, it is important to explore both hardware and software solutions for optimizing energy. The focus of high-level compiler optimizations has traditionally been on improving performance. In this paper, we present an experimental evaluation of several state-of-the-art high-level compiler optimizations on energy consumption, considering both the processor core (datapath) and memory system. This is in contrast to many of the previous works that have considered them in isolation.