Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Power-conscious high level synthesis using loop folding
DAC '97 Proceedings of the 34th annual Design Automation Conference
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Glitch power minimization by selective gate freezing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Influence of compiler optimizations on system power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
FPGA clock network architecture: flexibility vs. area and power
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
GlitchLess: an active glitch minimization technique for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Using negative edge triggered ffs to reduce glitching power in FPGA circuits
Proceedings of the 44th annual Design Automation Conference
Register transfer level power optimization with emphasis on glitch analysis and reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A routing approach to reduce glitches in low power FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA glitch power analysis and reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Net-length-based routability-driven power-aware clustering
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Location, location, location: the role of spatial locality in asymptotic energy minimization
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
| Hi-index | 0.00 |
This paper describes GlitchLess, a circuit-level technique for reducing power in field-programmable gate arrays (FPGAs) by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay elements to the logic blocks of the FPGA. After routing a circuit and performing static timing analysis, these delay elements are programmed to align the arrival times of the inputs of each lookup table (LUT), thereby preventing new glitches from being generated. Moreover, the delay elements also behave as filters that eliminate other glitches generated by upstream logic or off-chip circuitry. On average, the proposed implementation eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires little or no modifications to the routing architecture or computer-aided design (CAD) flow.