Glitch power minimization by selective gate freezing

Authors:
Luca Benini;Giovanni De Micheli;Alberto Macii;Enrico Macii;Massimo Poncino;Riccardo Scarsi
Affiliations:
Univ. di Bologna, Bologna, Italy;Stanford Univ., Stanford, CA;Politechnico di Torino, Twin, Italy;Politechnico di Torino, Twin, Italy;Politechnico di Torino, Twin, Italy;Politechnico di Torino, Torino, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Year:
2000

Citing 0
Cited 8

Retiming-based logic synthesis for low-power

Proceedings of the 2002 international symposium on Low power electronics and design
GlitchLess: an active glitch minimization technique for FPGAs

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
A low-power multiplier with the spurious power suppression technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A routing approach to reduce glitches in low power FPGAs

Proceedings of the 2009 international symposium on Physical design
A spurious-power suppression technique for multimedia/DSP applications

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design and analysis of a hybrid encoded low power multiplier with reduced transition activity technique

Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. Algorithms for gate selection and clustering that maximize the percentage of filtered glitches and reduce the overhead for generating the control signals are introduced. A power-efficient CMOS implementation of F-Gates is also described. An important feature of the proposed method is that it can be applied in place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.