Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Low-power design techniques for high-performance CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Glitch power minimization by selective gate freezing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Digital CMOS Design
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimization of switching activities of partial products for designing low-power multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
High-Performance Low-Power Left-to-Right Array Multiplier Design
IEEE Transactions on Computers
Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A low-power multiplier with the spurious power suppression technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Multiplication is an arithmetic process that is mostly used in Digital Signal Processing (DSP) and communication applications. Efficient implementation of the multipliers is required in many applications. The design of hybrid encoded low power multiplier with Reduced Transition Activity Technique (RTAT) is presented in this paper. The proposed encoding technique reduces the number of switching activity and dynamic power consumption by analyzing the bit patterns in the input data. In this proposed encoding scheme, the operation is executed depends upon the number of 1's and its position in the multiplier data. The architecture of the proposed multiplier is designed using a low power full adder which consumes less power than the other adder architectures. The switching activity of the proposed multiplier has been reduced by 86% and 46% compared with conventional and Booth multiplier respectively. It is observed from the device level simulation using TANNER 12.6 EDA that the power consumption of the proposed multiplier has been reduced by 87% and 26% compared with conventional and Booth multiplier.