Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Modern VLSI design: a systems approach
Modern VLSI design: a systems approach
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Practical low power digital VLSI design
Practical low power digital VLSI design
Low-energy CSMT carry generators and binary adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Low-Power CMOS Design
On reducing transition counts in sign detection circuits
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic functional unit assignment for low power
The Journal of Supercomputing
A low-power multiplier with the spurious power suppression technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A spurious-power suppression technique for multimedia/DSP applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Power reduction of superscalar processor functional units by resizing adder-width
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A technique to reduce static and dynamic power of functional units in high-performance processors
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2's complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2's complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.