Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ACM Transactions on Computer Systems (TOCS)
Reducing power with dynamic critical path information
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Design Challenges of Technology Scaling
IEEE Micro
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Picking Statistically Valid and Early Simulation Points
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper presents a hardware technique to reduce both the static and dynamic power consumption in Functional Units of a 64-bit superscalar processor. We have studied the instructions that require an adder and we can conclude that, in 64-bit processors, there are many instructions that do not require a 64-bit adder, and that by knowing the type of operation we can also know what adder type this instruction requires. This is due that there are some types of instruction where one of the two source operands is always narrow. Our approach is based on substituting some of the 64-bit power-hungry adders by others of 32-bit and 24-bits lower power-consumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring in a negligible performance penalty. We have tested four different configurations for the execution units in order to find which one obtains a higher reduction on power-consumption, preserving the performance of the processor. Our technique saves between 38,8% and a 54,1% of the power-consumption in the adders which is between 16,6% and a 23,1% of power-consumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units.