Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
Fast Multiplication Without Carry-Propagate Addition
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation
IEEE Transactions on Computers
Comments on Duprat and Muller's Branching CORDIC Paper
IEEE Transactions on Computers
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
An efficient signed digit montgomery multiplication for RSA
Journal of Systems Architecture: the EUROMICRO Journal
A new symbolic substitution based addition algorithm
Computers & Mathematics with Applications
Conventional adders with fine grained redundancy injection
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
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A novel hybrid number representation is proposed. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.