Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
The Case for a Redundant Format in Floating Point Arithmetic
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Reliable Binary Signed Digit Number Adder Design
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
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Many digital systems benefit implicitly or explicitly from redundant representations to improve their performance. In this work we present a Limited Selective Redundancy Injection (LSRI) method to improve arithmetic unit performance. Our results show that LSRI with Conventional Input Redundant Output (CI-RO) adder improves Ripple Carry Adder (RCA) latency and Power-Delay-Area-Product (PDAP) by about 50% for large operand size with less than 1% area overhead and slight improvement in the power consumption.