High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Carry-Free Addition of Recoded Binary Signed-Digit Numbers
IEEE Transactions on Computers
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Digital Filters and Signal Processing
Digital Filters and Signal Processing
Unifying carry-sum and signed-digital number representations for low power
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
IEEE Transactions on Computers
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
IEEE Transactions on Computers
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation
IEEE Transactions on Computers
Comments on Duprat and Muller's Branching CORDIC Paper
IEEE Transactions on Computers
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems
IEEE Transactions on Computers
Signed Digit Representations of Minimal Hamming Weight
IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
IEEE Transactions on Computers
Modular Arithmetic Using Low Order Redundant Bases
IEEE Transactions on Computers
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Compact non-binary fast adders using single-electron devices
Microelectronics Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
A new symbolic substitution based addition algorithm
Computers & Mathematics with Applications
An improved maximally redundant signed digit adder
Computers and Electrical Engineering
Conventional adders with fine grained redundancy injection
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
CORDIC architectures: a survey
VLSI Design
A loopless gray code for minimal signed-binary representations
ESA'05 Proceedings of the 13th annual European conference on Algorithms
Certain discrete dynamical systems, number systems and related integral self-affine sets
Theoretical Computer Science
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Decimal Division Algorithms: The Issue of Partial Remainders
Journal of Signal Processing Systems
| Hi-index | 15.02 |
Signed-digit (SD) number representation systems have been defined for any radix r驴3 with digit values ranging over the set (- alpha , . . ., -1, 0, 1, . . ., alpha ), where alpha is an arbitrary integer in the range 1/2r alpha r. Such number representation systems possess sufficient redundancy to allow for the annihilation of carry or borrow chains and hence result in fast propagation-free addition and subtraction. The author refers to the above as ordinary SD number systems and defines generalized SD number systems which contain them as a special symmetric subclass. It is shown that the generalization not only provides a unified view of all redundant number systems which have proven useful in practice (including stored-carry and stored-borrowed systems), but also leads to new number systems not examined before. Examples of such new number systems are stored-carry-or-borrow systems, stored-double-carry systems, and certain redundant decimal representations.