Comments on "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits"

Authors:
Behrooz Parhami
Affiliations:
-
Venue:
IEEE Transactions on Computers
Year:
1996

Citing 4
Cited 1

Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations

IEEE Transactions on Computers
On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems

IEEE Transactions on Computers
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits

IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications

IEEE Transactions on Computers

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

Journal of VLSI Signal Processing Systems

Quantified Score

Hi-index	14.98

Visualization

Abstract

Kawahito et al present multiplier designs using the binary-tree reduction feature of certain highly redundant radix-2 representations, along with multiple-valued current-mode circuit techniques, and show them to compare favorably to those based on less redundant binary signed-digit and carry-save numbers. We point out that these representation schemes, and their potential advantages, have been discussed in earlier publications and that a more general view of the parallel-carries addition process exploited in these multipliers leads to other potentially useful representations.