Computer number systems and arithmetic
Computer number systems and arithmetic
On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Arithmetic for an SVD processor
Journal of Parallel and Distributed Computing - Parallelism in Computer Arithmetic
Carry-Free Addition of Recoded Binary Signed-Digit Numbers
IEEE Transactions on Computers
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
IEEE Transactions on Computers
Carry-save architectures for high-speed digital signal processing
Journal of VLSI Signal Processing Systems - Parallel processing on VLSI arrays
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation
IEEE Transactions on Computers
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation
IEEE Transactions on Computers - Special issue on computer arithmetic
The CORDIC Algorithm: New Results for Fast VLSI Implementation
IEEE Transactions on Computers
On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems
IEEE Transactions on Computers
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
A Radix-10 BKM Algorithm for Computing Transcendentals on Pocket Computers
Journal of VLSI Signal Processing Systems - special issue on CORDIC
Fast CORDIC Algorithm Based on a New Recoding Scheme for Rotation Angles and Variable Scale Factors
Journal of VLSI Signal Processing Systems
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
Randomized Algorithms: A System-Level, Poly-Time Analysis of Robust Computation
IEEE Transactions on Computers
A Cordic-Based Processor Extension for Scalar and Vector Processing
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
P-CORDIC: a precomputation based rotation CORDIC algorithm
EURASIP Journal on Applied Signal Processing
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
CORDIC architectures: a survey
VLSI Design
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architecture for low latency radix-4 CORDIC
Computers and Electrical Engineering
VLSI architecture for parallel radix-4 CORDIC
Microprocessors & Microsystems
Hi-index | 14.99 |
The CORDIC algorithm is a well-known iterative method for the efficient computation of vector rotations, and trigonometric and hyperbolic functions. Basically, CORDIC performs a vector rotation which is not a perfect rotation, since the vector is also scaled by a constant factor. This scaling has to be compensated for following the CORDIC iteration.Since CORDIC implementations using conventional number systems are relatively slow, current research has focused on solutions employing redundant number systems which make a much faster implementation possible. The problem with these methods is that either the scale factor becomes variable, making additional operations necessary to compensate for the scaling, or additional iterations are necessary compared to the original algorithm.In contrast we developed transformations of the usual CORDIC algorithm which result in a constant scale factor redundant implementation without additional operations. The resulting "Differential CORDIC Algorithm" (DCORDIC) makes use of on-line (most significant digit first redundant) computation. We derive parallel architectures for the radix-2 redundant number systems and present some implementation results based on logic synthesis of VHDL descriptions produced by a DCORDIC VHDL generator. We finally prove that, due to the lack of additional operations, DCORDIC compares favorably with the previously known redundant methods in terms of latency and computational complexity.