On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Arithmetic for an SVD processor
Journal of Parallel and Distributed Computing - Parallelism in Computer Arithmetic
Carry-Free Addition of Recoded Binary Signed-Digit Numbers
IEEE Transactions on Computers
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation
IEEE Transactions on Computers
Bit-level systolic algorithms for real symmetric and Hermitian eigenvalue problems
Journal of VLSI Signal Processing Systems - Special issue: application specific array processors
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation
IEEE Transactions on Computers - Special issue on computer arithmetic
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors
IEEE Transactions on Computers
Redundant and On-Line CORDIC for Unitary Transformations
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Signal processing algorithms and architectures
Signal processing algorithms and architectures
Parallel singular value decomposition of complex matrices usingmultidimensional CORDIC algorithms
IEEE Transactions on Signal Processing
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
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A new high-speed redundant CORDIC processor is designed and implemented based on the double rotation method,which turns out to be the two-dimensional (2D) Householder CORDIC, a special case of the generalized Householder CORDIC in the 2D Euclidean vector space. The new processor has the advantages of regular structure and high throughput rate. The pipelined structure with radix-2 signed-digit (SD) redundant arithmetic is adopted to reduce the carry-propagation delay of the adderswhile the digit-serial structure alleviates the burden ofthe hardware cost and I/O requirement. Compared to previously proposed designs, the new CORDIC processor preserves the constant scaling factor, an important merit of theoriginal CORDIC, and thus does not require any complicated division or square-root operations for variable scaling factor calculation.Furthermore, the processor is well suited to VLSI implementation since itdoes not call for any irregularly inserted correcting iterations.Both angle calculation mode for computing trigonometric functionand vector rotation mode for plane rotations are supported.Practical VLSI chip implementation of the fixed-point redundantCORDIC processor using 0.6 μm standard cell library is given includingdetailed numerical error analysis.