Arithmetic for an SVD processor
Journal of Parallel and Distributed Computing - Parallelism in Computer Arithmetic
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
Expanding the Range of Convergence of the CORDIC Algorithm
IEEE Transactions on Computers
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation
IEEE Transactions on Computers
Bit-level systolic algorithms for real symmetric and Hermitian eigenvalue problems
Journal of VLSI Signal Processing Systems - Special issue: application specific array processors
Matrix computations (3rd ed.)
Computing Functions cos/sup -1/ and sin/sup -1/ Using CORDIC
IEEE Transactions on Computers
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors
IEEE Transactions on Computers
Signal processing algorithms and architectures
Signal processing algorithms and architectures
Algorithms for finite shift-rank processes
Algorithms for finite shift-rank processes
Multi-dimensional cordic algorithms
Multi-dimensional cordic algorithms
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems - special issue on CORDIC
A CORDIC based array architecture for complex discrete wavelet transform
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
Low latency word serial CORDIC
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics
IEEE Transactions on Computers
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Iterative QR decomposition architecture using the modified gram-schmidt algorithm for MIMO systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
Function approximation on decimal operands
Digital Signal Processing
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
Matrix computations are often expressed in terms of plane rotations, which may be implemented using COordinate Rotation DIgital Computer (CORDIC) arithmetic. As matrix sizes increase multiprocessor systems employing traditional CORDIC arithmetic, which operates on two-dimensional (2D) vectors, become unable to achieve sufficient speed. Speed may be increased by expressing the matrix computations in terms of higher dimensional rotations and implementing these rotations using novel CORDIC algorithms驴called Householder CORDIC驴that extend CORDIC arithmetic to arbitrary dimensions. The method employed to prove the convergence of these multi-dimensional algorithms differs from the one used in the 2D case. After a discussion of scaling factor decomposition, range extension and numerical errors, VLSI implementations of Householder CORDIC processors are presented and their speed and area are estimated. Finally, some applications of the Householder CORDIC algorithms are listed.