Discrete Basis and Computation of Elementary Functions
IEEE Transactions on Computers
Doubly pipelined Cordic array for digital signal processing algorithms
Journal of the Chinese Institute of Engineers
A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)
IEEE Transactions on Computers
A Fast Modified CORDIC—Implementation of Radial Basis Neural Networks
Journal of VLSI Signal Processing Systems
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors
IEEE Transactions on Computers
Redundant and On-Line CORDIC for Unitary Transformations
IEEE Transactions on Computers
IEEE Transactions on Computers
CORDIC Vectoring with Arbitrary Target Value
IEEE Transactions on Computers
Memory-efficient and high-performance 2-D DCT and IDCT processors based on CORDIC rotation
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Modular design and implementation of FPGA-based tap-selective maximum-likelihood channel estimator
WSEAS Transactions on Signal Processing
Fixed-Point Error Analysis of CORDIC Arithmetic for Special-Purpose Signal Processors
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
CORDIC architectures: a survey
VLSI Design
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence
Journal of Signal Processing Systems
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis
Journal of Signal Processing Systems
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The limitations on the numerical values of the functional arguments that are passed to the CORDIC computational units are discussed, with a special emphasis on the binary, fixed-point hardware implementation. Research in the area of expanding the allowed ranges of the input variables for which accurate output values can be obtained is presented. The methods proposed to expand the range of convergence for the CORDIC algorithm do not necessitate any unwidely overhead calculation, thus making this work amenable to a hardware implementation. The number of extra iterations introduced in the modified CORDIC algorithms is significantly less than the number of extra iterations discussed elsewhere. This reduction in the number of extra iterations will lead to a faster hardware implementation. Examples demonstrate the usefulness of the methods in realistic situations.