Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Expanding the Range of Convergence of the CORDIC Algorithm
IEEE Transactions on Computers
Special-purpose digital hardware for neural networks: an architectural survey
Journal of VLSI Signal Processing Systems
ASAP-a 2D DFT VLSI processor and architecture
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
New power-of-2 RNS scaling scheme for cell-based IC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intrinsic and extrinsic implementation of a bio-inspired hardware system
Information Sciences—Informatics and Computer Science: An International Journal - Special issue: Bio-inspired systems (BIS)
Hi-index | 0.00 |
This paper describes how the real-time bandwidth of a radialbasis neural network (RBNN) can be improved by the use of afield programmable gate array (FPGA). Accelerated performanceis gained by moving the time-consuming RBNN exponentialcalculations from a general purpose processor to a dedicatedFPGA that implements an optimized CORDIC-algorithm. Thedesign methodology is presented and illustrated with a speechrecognition application.