Numerical accuracy and hardware trade-offs for fixed-point CORDIC processor for digital signal processing system

  • Authors:
  • Tze-Yun Sung

  • Affiliations:
  • Department of Microelectronics Engineering, Chung Hua University, Hsinchu, Taiwan

  • Venue:
  • MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
  • Year:
  • 2007

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Abstract

In this paper, the complete error analysis of the conventional CORDIC (COordinate Rotation DIgital Computer) algorithm and the CORDIC with expanded convergence range is presented. All the computational error consisting of the approximation error and truncation error in both the rotation mode and vectoring mode has been derived systematically. It has been shown that the computation errors of CORDIC processor are dependent on the word length and number of iterations. The main contribution of this paper is a complete set of formulas describing the computation errors of CORDIC have been summarized in tabular form. By referring to these tables, one can design a cost-effective digital signal processing system using CORDIC processor in terms of areas and performances.