Carry-Free Addition of Recoded Binary Signed-Digit Numbers
IEEE Transactions on Computers
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation
IEEE Transactions on Computers
Low Latency Time CORDIC Algorithms
IEEE Transactions on Computers - Special issue on computer arithmetic
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation
IEEE Transactions on Computers - Special issue on computer arithmetic
Unified Mixed Radix 2-4 Redundant CORDIC Processor
IEEE Transactions on Computers
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm
IEEE Transactions on Computers
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation
IEEE Transactions on Computers
Low-energy CSMT carry generators and binary adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The CORDIC Algorithm: New Results for Fast VLSI Implementation
IEEE Transactions on Computers
IEEE Transactions on Computers
P-CORDIC: a precomputation based rotation CORDIC algorithm
EURASIP Journal on Applied Signal Processing
A Cordic Arithmetic Processor Chip
IEEE Transactions on Computers
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
CORDIC architectures: a survey
VLSI Design
The quantization effects of the CORDIC algorithm
IEEE Transactions on Signal Processing
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The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has been refined in terms of throughput and latency with the introduction of redundant arithmetic and higher radix techniques. In this paper, we propose a pipelined architecture using signed digit arithmetic for the VLSI efficient implementation of rotational radix-4 CORDIC algorithm, eliminating z path completely. A detailed comparison of the proposed architecture with the available radix-2 architectures shows the latency and hardware improvement. The proposed architecture achieves latency improvement over the previously proposed radix-4 architecture with a relatively small hardware overhead. The proposed architecture for 16-bit precision was implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesized for 16-bit precision with 90nm CMOS technology library and the area-time measures are provided. This architecture was also implemented using Xilinx ISE9.1 software and a Virtex device.