Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD
IEEE Transactions on Computers
A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms
Integration, the VLSI Journal
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Unified Mixed Radix 2-4 Redundant CORDIC Processor
IEEE Transactions on Computers
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm
IEEE Transactions on Computers
IEEE Transactions on Computers
High-Speed CORDIC Based on an Overlapped Architecture and a Novel σ-Prediction Method
Journal of VLSI Signal Processing Systems - special issue on CORDIC
Fast CORDIC Algorithm Based on a New Recoding Scheme for Rotation Angles and Variable Scale Factors
Journal of VLSI Signal Processing Systems
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Parallel Architecture for Fast Transforms with Trigonometric Kernel
IEEE Transactions on Parallel and Distributed Systems
Low latency word serial CORDIC
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
P-CORDIC: a precomputation based rotation CORDIC algorithm
EURASIP Journal on Applied Signal Processing
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
CORDIC architectures: a survey
VLSI Design
VLSI architecture for low latency radix-4 CORDIC
Computers and Electrical Engineering
VLSI architecture for parallel radix-4 CORDIC
Microprocessors & Microsystems
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Several methods for increasing the speed of the CORDIC algorithm are presented. First, an improved method which guarantees a constant scale factor when employing redundant addition schemes is developed. Then, an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described.