Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Redundant arithmetic, algorithms and implementations
Integration, the VLSI Journal
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
Journal of VLSI Signal Processing Systems
On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems
IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Reviewing 4-to-2 Adders for Multi-Operand Addition
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
A 40-ns 17-Bit by 17-Bit Array Multiplier
IEEE Transactions on Computers
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
An improved maximally redundant signed digit adder
Computers and Electrical Engineering
Improved CMOS (4;2) compressor designs for parallel multipliers
Computers and Electrical Engineering
Area Efficient Sequential Decimal Fixed-point Multiplier
Journal of Signal Processing Systems
Hi-index | 0.01 |
Hybrid-redundant number representation has provided a flexible framework for digit-parallel addition in a manner that facilitates area-time tradeoffs for VLSI implementations via arbitrary spacing of redundant digit positions within an otherwise nonredundant representation. We revisit the hybrid redundancy scheme, pointing out limitations such as representational asymmetry, lack of representational closure in certain adder implementations, and difficulties in subtraction and carry acceleration. Given the intuitiveness of the hybrid redundancy concept and its potential for describing practically useful redundant number systems, we are motivated to extend it within the framework of weighted bit-set encodings to circumvent the aforementioned problems. The extension is based mainly on allowing negatively weighted bits (negabits), as well as standard posibits, to appear in nonredundant positions. Our extended hybrid redundancy scheme provides for arbitrary spacing of redundant positions in symmetric digit sets, without any degradation in arithmetic efficiency, while at the same time allowing low-latency subtraction by means of the same circuitry that is used for addition. Finally, we describe how inverted encoding of negabits leads to the exclusive use of unmodified standard full/half-adder, counter, and compressor cells, with no extra inverters, and to the direct applicability of conventional carry acceleration techniques in constant-time addition.