Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
A High-Frequency Decimal Multiplier
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Decimal Multiplication with Efficient Partial Product Generation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
Decimal Adder with Signed Digit Arithmetic
IEEE Transactions on Computers
IBM POWER6 accelerators: VMX and DFU
IBM Journal of Research and Development
IEEE Transactions on Computers
Improving the Speed of Parallel Decimal Multiplication
IEEE Transactions on Computers
Improved Design of High-Performance Parallel Decimal Multipliers
IEEE Transactions on Computers
Decimal floating-point support on the IBM system z10 processor
IBM Journal of Research and Development
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
The IBM zEnterprise-196 Decimal Floating-Point Accelerator
ARITH '11 Proceedings of the 2011 IEEE 20th Symposium on Computer Arithmetic
High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
IEEE Transactions on Computers
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In this paper, a new architecture is proposed to reduce the area cost and power consumption of the decimal fixed-point multiplier. In the proposed sequential architecture, the partial product generation and selection cycles are reduced to one. Moreover, the elaborately selected easy multiples reduce the hardware requirement of the partial products selector. Subsequently, two partial products are accumulated with the iteration result in a redundant decimal format by a multi-operand redundant adder. The lower-significant half digits of the final product are iteratively converted in every cycle. On the other hand, the higher-significant half digits are converted by a carry-propagation adder in two extra cycles. After all, the area of the whole architecture is reduced significantly by not only the simpler partial product generation and accumulation architecture, but also the less registers. The synthesized result shows that the proposed sequential multiplier has a lower area cost and reasonable computation latency.