Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
On the Time Required to Perform Addition
Journal of the ACM (JACM)
Redundant arithmetic, algorithms and implementations
Integration, the VLSI Journal
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
Journal of VLSI Signal Processing Systems
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
The Case for a Redundant Format in Floating Point Arithmetic
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Reviewing 4-to-2 Adders for Multi-Operand Addition
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
A 40-ns 17-Bit by 17-Bit Array Multiplier
IEEE Transactions on Computers
Fully Redundant Decimal Arithmetic
ARITH '09 Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value
IEEE Transactions on Computers
Computer Arithmetic: Algorithms and Hardware Designs
Computer Arithmetic: Algorithms and Hardware Designs
A new construction adder based on Chinese abacus algorithm
Computers and Electrical Engineering
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Signed digit (SD) number systems support digit-parallel carry-free addition, where the sum digits absorb the possible signed carries in {-1,0,1}. Radix-2^h maximally redundant SD (MRSD) number systems are particularly attractive. The reason is that, with the minimal (h+1) bits per SD, maximum range is achieved. There are speculative MRSD adders that trade increased area and power for higher speed, via simultaneous computation of three sum digits, while anticipating one of the possible signed carries. However, the nonspeculative approach that uses carry-save two's complement encoding for intermediate sum digits, has proved to be more efficient. In this paper, we examine three previous nonspeculative MRSD adders and offer an improved design with significant savings in latency, area consumption and power dissipation. The enhanced performance is mainly due to the elimination of sign extension of the signed carries. The latter leads to a sum matrix of positively and negatively weighted bits that normally complicate the use of standard adder cells. However, with inverted encoding of negatively weighted bits, we manage to efficiently use such cells. The claimed performance measures are supported by 0.13@mm CMOS technology synthesis.