Computer arithmetic algorithms
Computer arithmetic algorithms
The Set Theory of Arithmetic Decomposition
IEEE Transactions on Computers
On recoding in arithmetic algorithms
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
IEEE Transactions on Computers
Approximating Elementary Functions with Symmetric Bipartite Tables
IEEE Transactions on Computers
Basic digit sets for radix representation
Journal of the ACM (JACM)
Redundant Radix Representations of Rings
IEEE Transactions on Computers
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
IEEE Transactions on Computers
Accurate Rounding Scheme for the Newton-Raphson Method Using Redundant Binary Representation
IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Faithful Bipartite ROM Reciprocal Tables
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
A complex-number multiplier using radix-4 digits
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Redundant Binary Booth Recoding
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
How Many Logic Levels Does Floating-Point Addition Require?
ICCD '98 Proceedings of the International Conference on Computer Design
Digit Selection for SRT Division and Square Root
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
An improved maximally redundant signed digit adder
Computers and Electrical Engineering
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Redundant notations are used implicitly or explicitly in many digital designs. They have been studied in details and a general framework is known to reduce the redundancy of a notation down to the minimally redundant digit set. We present here an operator to further reduce the redundancy of such a representation. It does not reduce the number of allowed digits since removing one digit to a minimally redundant digit set is a conversion to a non redundant digit set and this is an expensive operation. Our operator introduces some correlation between the digits to reduce the number of possible redundant notations for any represented number. This reduction is visible in small useful operators like the elimination of leading zeros. We also present a key application with a CMOS Booth recoded multiplier. Our multiplier is able to accept both a redundant or a non redundant input with very little modifications and almost no penalty in time or space compared to state-of-the-art non redundant multipliers.