A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
An improved maximally redundant signed digit adder
Computers and Electrical Engineering
Conventional adders with fine grained redundancy injection
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This work uses a partially redundant number system as an internal format for floating point arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder using the proposed format is presented and the specific challenges of the design are explained. A brief description of a multiplier and divider using the proposed format is also presented. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard. Transistor simulation of the adder and multiplier confirm the performance advantage predicted by the analytical model.