Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Redundant arithmetic, algorithms and implementations
Integration, the VLSI Journal
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
The Case for a Redundant Format in Floating Point Arithmetic
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
A High-Frequency Decimal Multiplier
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
High-Speed Multioperand Decimal Adders
IEEE Transactions on Computers
Decimal Multiplication with Efficient Partial Product Generation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Fast decimal floating-point division
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
IEEE Transactions on Computers
A New Family of High.Performance Parallel Decimal Multipliers
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
A Decimal Floating-Point Divider Using Newton---Raphson Iteration
Journal of VLSI Signal Processing Systems
Decimal Adder with Signed Digit Arithmetic
IEEE Transactions on Computers
IEEE Transactions on Computers
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach
IEEE Transactions on Computers
A New Representation for Decimal Numbers
IEEE Transactions on Computers
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
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Decimal computer arithmetic is experiencing a revived popularity, and there is quest for high-performance decimal hardware units. Successful experiences on binary computer arithmetic may find grounds in decimal arithmetic. For example, the traditional fully redundant (i.e., the result and both of the operands are represented in a redundant format) and semi-redundant (i.e., the result and only one of the operands are redundant) binary addition schemes have influenced the design and implementation of similar decimal arithmetic units. However, special comparison and correction steps are required when decimal arithmetic algorithms are implemented on binary hardware. To circumvent these difficulties, alternative encodings of decimal digits and a variety of decimal arithmetic algorithms have been examined by many researchers over decades. In this paper we offer a new redundant decimal digit set [-8, 9] and a fully redundant addition/subtraction scheme. The proposed digit set, faithfully encoded as a mix of posibits, negabits, and unibits, is shown to obviate the need for any compare-to-9 operations and leads to minimal penalty subtraction using the addition circuitry. Moreover, conversion from the standard BCD encoding to the proposed stored-unibit encoding is possible with the latency of one logic level. However, the reverse conversion, like any other redundant to nonredundant conversion, involves carry propagation.