Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Readings in computer architecture
Readings in computer architecture
Reviewing 4-to-2 Adders for Multi-Operand Addition
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
IEEE Transactions on Computers
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach
IEEE Transactions on Computers
A BCD-based architecture for fast coordinate rotation
Journal of Systems Architecture: the EUROMICRO Journal
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
Error-free algorithm and architecture of radix-10 logarithmic converter
Computers and Electrical Engineering
Delay-based processing-in-wire for design of QCA serial decimal arithmetic units
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 14.99 |
There is increasing interest in hardware support for decimal arithmetic as a result of recent growth in commercial, financial, and Internet-based applications. Consequently, new specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic. This paper introduces and analyzes three techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Two of the techniques speculate BCD correction values and correct intermediate results while adding the input operands. The first speculates over one addition. The second speculates over two additions. The third technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next more significant digit. Multioperand adder designs are constructed and synthesized for four to 16 input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to several previous techniques for high-speed decimal addition.