Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
A Decimal Floating-Point Specification
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Decimal Floating-Point Division Using Newton-Raphson Iteration
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
High-Speed Multioperand Decimal Adders
IEEE Transactions on Computers
Decimal Multiplication with Efficient Partial Product Generation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods
IEEE Transactions on Computers
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
A combined decimal and binary floating-point divider
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
A study of decimal left shifters for binary numbers
Information and Computation
Decimal Division Algorithms: The Issue of Partial Remainders
Journal of Signal Processing Systems
Hi-index | 14.98 |
In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for {\rm radix}{\hbox{-}}2^{k} dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix--10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significands) and it has a shorter latency than a radix-10 unit based on the Newton-Raphson approximation.