Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Computer arithmetic algorithms
Computer arithmetic algorithms
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Low Power Digital CMOS Design
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
ICCD '98 Proceedings of the International Conference on Computer Design
Boosting Very-High Radix Division with Prescaling and Selection by Rounding
IEEE Transactions on Computers
A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root
IEEE Transactions on Computers
Digit-Recurrence Dividers with Reduced Logical Depth
IEEE Transactions on Computers
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
IEEE Transactions on Computers
Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling
Proceedings of the conference on Design, automation and test in Europe
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The general objective of our work is to develop methods to reduce the energy consumption of arithmetic modules while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here, we illustrate some techniques for dividers realized in CMOS technology. The energy dissipation reduction is carried out at different levels of abstraction: from the algorithm level down to the implementation, or gate, level. We describe the use of techniques such as switching-off not active blocks, retiming, dual voltage, and equalizing the paths to reduce glitches. Also, we describe modifications in the on-the-fly conversion and rounding algorithm and in the redundant representation of the residual in order to reduce the energy dissipation. The techniques and modifications mentioned above are applied to a radix-4, divider, realized with static CMOS standard cells, for which a reduction of 40 percent is obtained with respect to the standard implementation. This reduction is expected to be about 60 percent if low-voltage gates, for dual voltage implementation, are available. The techniques used here should be applicable to a variety of arithmetic modules which have similar characteristics