Computer arithmetic algorithms
Computer arithmetic algorithms
The Electronic Numerical Integrator and Computer (ENIAC)
IEEE Annals of the History of Computing
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
High-Speed Multioperand Decimal Adders
IEEE Transactions on Computers
IEEE Transactions on Computers
Iterative Arrays ror Radix Conversion
IEEE Transactions on Computers
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
Error-free algorithm and architecture of radix-10 logarithmic converter
Computers and Electrical Engineering
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Decimal arithmetic has been in recent years revived due to the large amount of data in commercial applications. We consider the problem of Multi Operand Parallel Decimal Addition with an approach that uses binary arithmetic, suggested by the adoption of BCD numbers. This involves corrections in order to obtain the BCD result, or a binary to decimal conversion. We adopt the latter approach, particularly efficient for a large number of addends. Conversion requires a relatively small area and can afford fast operation. The BD conversion, moreover, allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spreadsheets have been developed for adding several BCD digits and for simulating the binary to decimal conversion as design tool.