Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Design issues in high performance floating point arithmetic units
Design issues in high performance floating point arithmetic units
Division Algorithms and Implementations
IEEE Transactions on Computers
Powering by a Table Look-Up and a Multiplication with Operand Modification
IEEE Transactions on Computers
Microsoft C# Language Specifications
Microsoft C# Language Specifications
Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
Rounding for Quadratically Converging Algorithms for Division and Square Root
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
An Analysis of Division Algorithms and Implementations
An Analysis of Division Algorithms and Implementations
Proceedings of the 31st annual international symposium on Computer architecture
Decimal Floating-Point Division Using Newton-Raphson Iteration
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
POWER4 system microarchitecture
IBM Journal of Research and Development
Modular array structure for non-restoring square root circuit
Journal of Systems Architecture: the EUROMICRO Journal
Fully redundant decimal addition and subtraction using stored-unibit encoding
Integration, the VLSI Journal
A combined decimal and binary floating-point divider
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
A study of decimal left shifters for binary numbers
Information and Computation
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Increasing chip densities and transistor counts provide more room for designers to add functionality for important application domains into future microprocessors. As a result of rapid growth in financial, commercial, and Internet-based applications, hardware support for decimal floating-point arithmetic is now being considered by various computer manufacturers and specifications for decimal floating-point arithmetic have been added to the draft revision of the IEEE-754 Standard for Floating-Point Arithmetic (IEEE P754). In this paper, we presents an efficient arithmetic algorithm and hardware design for decimal floating-point division. The design uses an efficient piecewise linear approximation, a modified Newton---Raphson iteration, a specialized rounding technique, and a simplified decimal incrementer and decrementer. Synthesis results show that a 64-bit (16-digit) implementation of the decimal divider, which is compliant with the current version of IEEE P754, has an estimated critical path delay of 0.69 ns (around 13 FO4 inverter delays) when implemented using LSI Logic's 0.11 micron Gflx-P standard cell library.