High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
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IEEE Transactions on Computers
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms
ISMVL '03 Proceedings of the 33rd International Symposium on Multiple-Valued Logic
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IEEE Transactions on Computers
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On single-electron technology full adders
IEEE Transactions on Nanotechnology
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IEEE Transactions on Nanotechnology
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IEEE Transactions on Nanotechnology
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IEEE Transactions on Nanotechnology
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Neural Networks
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This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits: the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders.