Glitch power minimization by selective gate freezing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimization of switching activities of partial products for designing low-power multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Dynamic voltage and frequency scaling based on workload decomposition
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power fixed-width array multipliers
Proceedings of the 2004 international symposium on Low power electronics and design
A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
High-Performance Low-Power Left-to-Right Array Multiplier Design
IEEE Transactions on Computers
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
IEEE Transactions on Computers
Low-power VLSI design for motion estimation using adaptive pixel truncation
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC in wireless environments
IEEE Transactions on Circuits and Systems for Video Technology
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Design of power-efficient configurable booth multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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This paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. This paper adopts two multimedia/DSP design examples, i.e., a multitransform design for H.264 and a versatile multimedia functional unit (VMFU), to evaluate the proposed SPST. These two design examples have quite different hardware configurations, thus, the realization issues of the SPST on every design also remarkably differ from each other. The multitransform design can compute three transforms which are required in H.264 encoding while the VMFU possesses six commonly used multimedia/DSP functions, namely, addition, subtraction, multiplication, MAC, interpolation, and sum-of-absolute-difference. After optimizing the design elaborately, we find that the proposed SPST can, respectively, save 27% and 24% power dissipation on average of the H.264 multitransform design and the VMFU at the expense of less than 20% area augmentation.